As performance of LSI chips such as CPU has been improved, processing speed of electronic devices has been up and volume of data handled by the electronic devices have been continuously increased. In view of such a background, various techniques have been developed to transmit large-volume data at high speed using a small number of signal lines.
LVDS (Low Voltage Differential Signal) is typical of such techniques. LVDS achieves a transmission speed of about 3 Gbps, but transmission speed higher than 3 Gbps has been requested in many cases recently. Upon such a request, a high-speed transmission system called CML (Current Mode Logic) has been developed.
On the other hand, there is a demand for reducing power consumption as much as possible by reducing the voltage magnitude in transmission, in priority to improvement of transmission speed. LVDS is not necessarily an optimum transmission system in terms of the reduction in power consumption.
As a technique to fulfill the demands for high-speed transmission and lower power consumption conflicting with each other, a technique of switching between LVDS and CML has been proposed. However, this technique is not excellent in terms of power consumption since LVDS itself requires high power consumption and CML further increases the high power consumption.